Hardware Implementation of the Compression Function for Selected SHA-3 Candidates
نویسندگان
چکیده
Hardware implementation of the main building block (compression function) for five different SHA-3 candidates is presented. The five candidates, namely Blue Midnight Wish, Luffa, Skein, Shabal, and Blake have been considered since they present faster software implementation results compared to the rest of the SHA-3 proposals. The compression functions realized in hardware create the message digest of size 256 bits. We report both ASIC and FPGA implementations. The results allow an easy comparison for hardware performance of the candidates.
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